The present invention relates to a clock signal generator circuit for video signals, and more particularly to a clock generator circuit for generating a clock signal which is used with digital circuits in a video tape recorder, television receiver, projector and the like, with a write circuit for a liquid crystal panel, or with other circuits.
For digital circuits in a television receiver, tape recorder and the like, it is necessary to use a clock signal synchronized with a synchronous signal for video signals, the clock signal having, for example, a frequency of 910 f.sub.H (f.sub.H is the frequency of a horizontal synchronous signal), 1820 f.sub.H or the like. FIG. 1 shows the arrangement of a conventional clock generator circuit for generating such a clock signal.
Referring to FIG. 1, reference numeral 1 represents a monostable multivibrator (hereinafter abbreviated as MM) which is triggered by a synchronous signal contained in an input video signal and generates a pulse in synchronism with the synchronous signal. A sample/hold (hereinafter abbreviated as S/H) circuit samples and holds a trapezoid signal outputted from a trapezoid signal generator circuit 3, at the timing of an output pulse from MM 2. A low-pass filter (hereinafter abbreviated as LPF) 4 smoothes an output from S/H circuit 2. A voltage control oscillator (hereinafter abbreviated as VCO) 5 generates clock signals having a frequency corresponding to an output from LPF 4. A counter 6 frequency-divides clock signals outputted from VCO 5. A phase-locked loop circuit (hereinafter abbreviated as PLL circuit) 7 is constructed of S/H circuit 2, LPF 4, VCO 5, counter 6 and trapezoid signal generator circuit 3.
When PLL circuit 7 receives a pulse in synchronism with the horizontal synchronous signal contained in an input video signal, it generates a clock signal in synchronism with the phase of the synchronous signal.
With a conventional circuit constructed as above, MM 1 is triggered by a synchronous signal contained in a video signal, and an output signal from MM 1 drives PLL circuit 7. Therefore, as shown in FIG. 2(a), even a dubbing preventing signal having a synchronous tip level component is detected as a synchronous signal which is used then to drive PLL circuit 7. During such period, the frequency of a clock signal is disturbed, thereby posing some problem such as a skew curve in a frame image or erroneous digital processing operation.
Like problems also occur for the case of equalizing pulses during the vertical blanking period. Further, in generating a clock signal in synchronism with a video signal reproduced from a video tape recorder, there is also associated with an erroneous operation because of skews or noises generated upon switching of a rotary head.